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RF/IF 34dB Gain Range VGA with AGC Detector
Preliminary Technical Data
FEATURES
Analog Variable Gain Range: -12 to 22dB Linear-in-dB Scaling: 40dB/V 3dB Bandwidth: 800 MHz Integrated RMS Detector Output 1dB Compression: 17 dBm Output IP3: 33.7 dBm Minimum Noise Figure: 9 dB Input and Output Impedances: 50 ohms Single Supply Voltages from 4.5 - 5.5 V RoHS Compliant 24-lead LFCSP Package
AD8368
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS
Complete IF AGC Amplifiers Gain Trimming and Leveling Cellular base station Point-to-Point Radio links RF Instrumentation
Figure 1.
GENERAL DESCRIPTION
The AD8368 is a variable gain amplifier with analog linearin-dB gain control that can be used from low frequencies to beyond 1 GHz. Its excellent gain range, conformance and flatness are attributed to Analog Devices' X-AMP TM architecture, an innovative technique for implementing high performance variable gain-control. The gain range of -12 to 22 dB is scaled accurately to 40 dB/V with excellent conformance error. The AD8368 has a 3-dB bandwidth of 800 MHz that is independent of gain setting. At 70 MHz, the OIP3 and P1dB are 33.7 dBm and 17 dBm, respectively. The output noise floor is -143 dBm/Hz, which corresponds to 9 dB noise figure at maximum gain. The single-ended input and output impedances are nominally 50 ohms. The gain of the AD8368 can be configured to be an increasing or decreasing function of the gain control voltage depending on whether the MODE pin is pulled to the positive supply or to ground, respectively. When MODE is pulled high, the gain increases with gain control voltage and the AD8368 operates as a typical VGA. When MODE is pulled low, the gain decreases with gain control voltage. This second mode allows the AD8368 to be used in AGC systems
Rev. PrB
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
with power detectors whose outputs increase with received signal level. The AD8368 contains an accurate stand-alone RMS detector that enables versatile AGC operation. To form a complete AGC loop, the MODE pin is pulled low and the detector output pin is directly connected to the GAIN pin and an integrating capacitor. Then, by connecting the VGA output OUTP directly to the detector input DETI, the output is leveled to the set-point of 63 mVrms or -11 dBm referenced to 50 . This reference level can be raised by dividing down the output signal before applying it to DETI. The detector can level the AD8368 output or any other point in the signal chain depending on where the detector pins DETI and DETO are connected. The AD8368 operates from a supply voltage of 4.5 to 5.5 V and consumes 54 mA of current. It can be fully powered down to <1mA by grounding the ENBL pin. The AD8368 is fabricated in Analog Devices' proprietary SiGe SOI complementary bipolar IC process. It is available in a 24 pin CSP and operates over the industrial temperature range of - 40 to 85 C. Application boards are available upon request.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. www.analog.com Tel: 781.329.4700 Fax: 781.461.3113 (c) 2005 Analog Devices, Inc. All rights reserved.
AD8368
Preliminary Technical Data
AD8368-SPECIFICATIONS
Parameter POWER INTERFACE Supply Voltage Total Supply Current Disable Current vs. Temperature SQUARE LAW DETECTOR ENBL high ENBL low Conditions
(VS=5V, T=25C, System Impedance Zo = 50, MODE = 5V unless otherwise noted)
Min
Typ
Max
Units
4.5 54 1.0 TBD
5.5
V mA mA
-40C TA 85C
TBD
mA
Output Set-point Input DC Level Input Impedance
OUTP connected to DETI DETI pin DETI pin
-11 Vp/2 710 0.6
dBm V Ohm pF Vp/2 V us
Output Range AGC Small-signal Response MODE CONTROL INTERFACE (MODE) Mode LO Threshold Mode HI Threshold Input Current ENABLE INTERFACE (ENBL) Enable Threshold Enable Response Time
DETO pin CDETO=5pF
0 1
Device in negative slope mode of operation Device in positive slope mode of operation
TBD TBD TBD
V V uA
2.5 Time delay following HI to LO transition until device meets full specifications. ENBL = 5 V ENBL = 0 V 1.5
V s
Enable Input Bias Current
TBD TBD
A nA
Rev. PrB | Page 2 of 13
Preliminary Technical Data
AD8368
AD8368 SPECIFICATIONS
Parameter OVERALL FUNCTION Frequency Range Maximum Input Maximum Output Input Resistance Output Resistance GAIN CONTROL INTERFACE (GAIN) GAIN Span GAIN Scaling Conditions
(VS=5V, T=25C, System Impedance Zo = 50 , MODE = 5V unless otherwise noted)
Min
Typ
Max
Units
LF To Avoid Input Overload To Avoid Clipping From INPT to ICOM From OUTP to OCOM 3 2 50 50
1000
MHz Vp Vp
34 MODE = 5 V, 50 mV VGAIN 950 mV MODE = 0 V, 50 mV VGAIN 950 mV 37.16 -37.5 0.4 22 -12 0 From 0 dB to 30 dB From 30 dB to 0 dB TBD TBD 10 1
dB dB/V dB/V dB dB dB V ns ns kohm
Gain Accuracy Maximum Gain Minimum Gain VGAIN Voltage Range Gain Step Response
100 mV VGAIN 900 mV VGAIN = 1 V VGAIN = 0 V
Input Impedance f = 70 MHz Noise Figure Output IP3 Output 1dB Compression Point f = 140 MHz Noise Figure Output IP3 Output 1dB Compression Point f = 240 MHz Noise Figure Output IP3 Output 1dB Compression Point
From GAIN To ICOM
Maximum Gain f1 = 70 MHz, f2 = 71 MHz, VGAIN = 1 V VGAIN = 1 V
9 33.7 17
dB dBm dBm
Maximum Gain f1 = 140 MHz, f2 = 141 MHz, VGAIN = 1 V VGAIN = 1 V
9 31.6 13
dB dBm dBm
Maximum Gain f1 = 240MHz, f2 = 241 MHz, VGAIN = 1 V VGAIN = 1 V
9 29 15
dB dBm dBm
Rev. PrB | Page 3 of 13
AD8368
f = 380 MHz Noise Figure Output IP3 Output 1dB Compression Point Maximum Gain f1 = 380 MHz, f2 = 381 MHz, VGAIN = 1 V VGAIN = 1 V
Preliminary Technical Data
9 24.8 9 dB dBm dBm
Rev. PrB | Page 4 of 13
Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS
Table 1.
Parameter Supply Voltage, VPSO, VPSI ENBL and MODE Select Voltage RF Input Level Internal Power Dissipation JA Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature Range (Soldering 60 sec) Rating TBD V VPS+TBDmV 20 dBm TBD mW TBD C/W 135C -40C to +85C -65C to +150C 300C
AD8368
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrB | Page 5 of 13
AD8368 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Preliminary Technical Data
Figure 2. 24-Lead LFCSP
Table 2. Pin Function Descriptions
Pin 1 2 3 4,14,15 Name GAIN DETO HPFL DECL Function Gain Control Voltage Input Detector Output. Provides output current for RSSI function and AGC control. High Pass Filter Connection. A capacitor to ground sets the corner frequency of the output offset control loop. Decoupling Pin. Can Be Used to Modify the Output Reference Level. ~VPS/2 5 6,7,16, 17,18,20 8 9,10,11, 12,13,22, 23 19 21 24 INPT MODE ENBL Signal Input. Must be AC coupled Gain Direction Control. HI for Positive Slope. LO for Negative Slope. Apply a positive voltage ( VS ) to activate device. DETI OCOM ICOM OUTP VPSO VPSI Detector Input Common. Connect to low impedance ground. ICOM and OCOM are tied together internally with back to back PN junctions. They should be tied together externally and properly grounded. Signal Output. Must be AC coupled. Positive Supply Voltage. +4.5 V to +5.5 V. VPSI and VPSO are tied together internally with back to back PN junctions. They should be tied together externally and properly bypassed.
Rev. PrB | Page 6 of 13
Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS
VS=5V, T=25C, System Impedance Zo = 50 , MODE = 5V unless otherwise noted
25 20 15 10
VGAIN = 1000mV
AD8368
0 -10 -20
Reverse Isolation - dB
VGAIN = 800mV
-30 -40 -50
VGAIN = 0, 200, 400, 600, 800, 1000mV
Gain - dB
VGAIN = 600mV
5 0 -5
VGAIN = 200mV VGAIN = 400mV
-60 -70 -80 -90
-10
VGAIN = 0mV
-15 0 200 400 600 800 1000
-100 0 200 400 600 800 1000
Freq - MHz
Freq - MHz
Figure 3. Gain vs. Frequency
0 -5 -5 -10 -15
VGAIN = 800mV
Figure 6. Reverse Isolation vs. Frequency
0
Output Return Loss - dB
Input Return Loss - dB
VGAIN = 1000mV
VGAIN = 0, 200, 400, 600, 800, 1000mV
-10
-20
VGAIN = 600mV
-15
-25
VGAIN = 400mV
-30
VGAIN = 200mV
-20
-35
VGAIN = 0mV
-25
-40 -45 0 200 400 600 800 1000 -30 0 200 400 600 800 1000
Freq - MHz
Freq - MHz
Figure 4. Input Return Loss vs. Frequency
35 -135
40 35
Figure 7. Output Return Loss vs. Frequency
OIP3, Noise Figure - dBm , dB
33
-137 Noise Floor - dBm/Hz
30
OIP3
OIP3 - dBm
31
-139
25 20 15 10
NF
29
-141
27
-143
5
25 0 200 400 600 800
-145 1000
0 0 100 200 300 400 500 600 700 800
VGAIN - V
Freq - MHz
Figure 5. OIP3 and Output Noise Floor vs. VGAIN at 140MHz
Figure 7.OIP3 and NF vs. Frequency
Rev. PrB | Page 7 of 13
AD8368 CIRCUIT DESCRIPTION
The AD8368 is a single-ended VGA with a bandwidth of 800MHz and a gain control range of 32dB from -10dB to +22dB. It also includes an onboard square-law detector that can be used as a standalone detector, or in an AGC loop with the VGA. Using Analog Devices' patented X-AMP architecture, the AD8368 achieves accurate linear-in-dB gain control. The part is designed with 50 input and output impedances. The main signal path consists of a variable input attenuator followed by an integrator and output buffer. Feedback around the integrator creates a fixed-gain amplifier. See Figure 8 for a block diagram of the part.
Preliminary Technical Data
requires an external decoupling capacitor. Since the fixed-gain amplifier and output stage have an extremely large overall gain, small DC offsets at the input of the fixed-gain amplifier could lead to large output offsets. To correct for this problem over Vgain, supply and temperature variations, a low-pass offset correction loop (see Figure 9) is used which senses and maintains the output DC level at the voltage on the DECL pin. The low-pass corner frequency of this loop is controlled by the size of the capacitor on the HPFL pin.
Figure 9. Output Centering Control Loop Input and Output Impedances The input to the AD8368 should be externally AC coupled to prevent disrupting the DC levels on the chip. Thus, a sufficiently large coupling capacitor should be used such that the series impedance of the capacitor is negligible at the frequencies of interest. On the chip, the input is connected directly to a resistor ladder network whose impedance is nominally 50 . The output of the part should also be AC coupled to prevent disrupting the output DC level. As with the input, a sufficiently large value of capacitance should be used so that the series impedance of the capacitor is negligible at the frequencies of interest. The fixed gain of the rail to rail output buffer combined with the resistive feedback from output to input provides a nominally 50- output impedance.
Figure 8. Simplified Block Diagram Input Attenuator and Interpolator The input attenuator is built from a resistor ladder with 18 -2dB tap points. Each of these tap points is fed into separate variable transconductance (gm) stages, whose outputs are summed and fed into an integrator. Gain control is achieved by using the GAIN pin to control the interpolator. As GAIN is swept from 0V to 1V, the interpolator selects different tap points by varying the transconductance of the gm stages. For gains between two tap points, the interpolator varies the transconductance such that the weighted sum of several adjacent tap points are chosen. In this way, an accurate continuous linear-in-dB gain control response is produced. Integrator and Output Buffer The current outputs of the gm stages are summed and fed into an integrator. Resistive feedback from the output of the integrator to the gm stages creates a low-noise, high-linearity fixed-gain amplifier. The output of this amplifier is fed into the output buffer which provides an active 50 output and additional 6dB of fixed gain. Output DC level and offset correction Since the AD8368 is single-ended, the DC levels at the input and output are regulated to VPSI/2 by an internal regulator. The output of this regulator is connected to the DECL line and
Gain Control Interface
The AD8368 has a linear-in-dB gain control interface that can be operated in either a gain-up or gain-down mode. In the gain-up mode with the MODE pin pulled high, the gain increases with increasing GAIN voltages. In gain-down mode, with the MODE pin pulled low, the gain decreases with increasing GAIN voltages. Ideally, with MODE pulled high, the ideal gain function is given by the equation,
Gain(dB) = 37 x VGAIN - 14
Rev. PrB | Page 8 of 13
Preliminary Technical Data
With MODE pulled low, the ideal gain function is given by the equation,
VIN VPOS
AD8368
Gain(dB) = -37.5 x VGAIN + 24.8
where VGAIN is expressed in Volts in both above equations.
VGAIN 0 to 1V
ENBL GAIN
VPSI
VPSI
MODE
ICOM
INPT ICOM
DETO
70MHz, Vgain and Error
ICOM
HPFL
3 2.5 2 1.5 1 0.5 Error (dB) 0 -0.5 -1 -1.5 -2 -2.5 -3 0 0.1 0.2 0.3 0.4 0.5 Vgain (V) 0.6 0.7 0.8 0.9 1 25 22.5 20 17.5 15 12.5 10 7.5 5 2.5 0 -2.5 -5 -7.5 -10 -12.5 -15 ERROR_H ERROR_L GAIN_H GAIN_L
ICOM
X2
DECL
REF
DECL
DETI OCOM OCOM OUTP
DECL
AD8368
VPSO VPSO VPSI
VPSI VPSI
VPOS VOUT
Figure 11. Typical Connections for VGA Mode The MODE pin controls whether the gain of the part is an increasing or decreasing function of the GAIN voltage. When the MODE pin is high, the gain increases with increasing GAIN voltages. When the MODE pin is low, the gain decreases with increasing GAIN voltages. The ENBL pin is used to enable or disable the part. When ENBL is high, the part is enabled. With ENBL low, the part is disabled and draws a fraction of the normal supply current. The DECL pin should be decoupled using a large capacitor so that DECL acts as an AC ground. The HPFL pin is used to control the low-pass corner frequency of the output offset correction loop. The high pass corner frequency is inversely proportional to the HPFL bypass capacitor.
Figure 10 The gain function can be either an increasing or decreasing function of VGAIN, depending on the MODE pin. It should be noted that gain-down mode is the gain mode required to use the onboard detector and VGA together as an AGC loop.
VGA Operation
The AD8368 is a general-purpose VGA suitable for use in a wide variety of applications where voltage-control of gain is needed. While having a 800 MHz bandwidth, its use is not limited to high frequency signal processing. Its accurate, temperature- and supply-stable linear-in-dB scaling will be valuable wherever it is important to have a more dependable response to the control voltage than is usually offered by VGAs of this sort. The typical connections for using the AD8368 in VGA mode are illustrated in Figure 11. The input (INPT) and output (OUTP) of the AD8368 should be externally AC coupled to prevent disrupting the DC levels on the chip. Thus, a sufficiently large coupling capacitor should be used such that the series impedance of the capacitor is negligible at the frequencies of interest.
AGC Operation
The AD8368 may be used as an AGC amplifier as shown in Figure 12. For this application, the accurate internal square-law detector is employed. The output of this detector is a current that varies in polarity depending on whether the rms value of the output is greater or less than its internally-determined"setpoint" of 63mVrms. This is 178mV pk-pk for sine-wave signals, but the peak amplitude for other signals, such as Gaussian noise, or those carrying complex modulation, will be invariably be somewhat greater. However, for all waveforms having a reasonable crest factor (less than 13dB), the rms value will be correctly measured and delivered at VOUT. The output setpoint may be adjusted using an external resistive divider network as depicted in Figure y. In this configuration the RMS output voltage will be equal to (1+n)63mVrms, where n=R2/R1. For the default set-point of 63mVrms simply short R1 (direct connection from OUTP to DETI) and remove R2.
Rev. PrB | Page 9 of 13
AD8368
3
Preliminary Technical Data
2.5
2
RSSI - V
1.5
1
0.5
0 -40 -30 -20 -10 0 10 20
Power In - dBm
Figure 12. AGC Mode of Operation
The AGC mode of operation requires that the correct gain direction is chosen. Specifically, the gain must fall as VAGC increases to restore the needed balance against the set-point. Therefore, the MODE pin must be pulled low. This very accurate leveling function is shown in Figure 13, where the rms output is held to within 0.2 dB of the set point for >30 dB range of input levels. This measurement was made using R1 = 100 ohms and R2 = 226 ohms to achieve 0 dBm output level. A valuable feature of using a square law detector is that the RSSI voltage is a true reflection of signal power, and may be converted to an absolute power measurement for any given source impedance. The AD8368 may be employed as a true-power meter by monitoring the voltage present at the DETO/GAIN interface.
Figure 14. Monitoring the GAIN/DETO RSSI Voltage versus Input Power.
10 9 8 7 6 5 4 3 2 1 0
EVM - %
Figure 15 illustrates the measured error-vector-magnitude (EVM) performance for a 16-QAM modulation at 10MSymbols/sec using CDETO=1000pF. At lower symbol rates the AGC loop could start to track the peak to peak transitions due to the modulation. At lower symbol rates it may be necessary to slow down the response of the AGC loop by increasing the value of CDETO .
10 5 0
-40
-30
-20
-10
0
10
20
Power In - dBm
Figure 15. Error Vector Magnitude Performance for 16-QAM 10Msymbols/sec.
Power Out - dBm
-5 -10 -15 -20 -25 -30 -40 -30 -20 -10 0 10 20
Power In - dBm
Figure 13 Output Power versus Input Power in AGC Mode at 140MHz.
Rev. PrB | Page 10 of 13
Preliminary Technical Data
EVALUATION BOARD
AD8368
Table X. Evaluation Board Configuration Options Component R1, R2 R10 R11 , R12 , C10 , C11 , C12 , C13 , C14 , C15 Function Pull down resistors for mode and enable Jumper resistors Supply decoupling. Jumpers and power supply decoupling resistors and filter capacitors. Default Conditions R1 = R2 = 10 k R10 = 0 R11 = R12 = 0 C11 = C12 = 1 nF C13 = C14 = C15 = 0.1 uF
CIN
RF input. Cin provides dc block for RF input.
CIN = 10 nF
COUT
RF output. Cin provides dc block for RF output. Feedback path for AGC operation. For default set point of 63mVrms set R31 = 0 and remove R32. For other AGC setpoints the RMS voltage output is determined from (1+n)63mVrms. Where n = R31/R32.
Rev. PrB | Page 11 of 13
COUT = 10 nF
R31, R32
R31 = OPEN (VGA mode)
AD8368
R35 Detector out RSSI voltage
Preliminary Technical Data
R35 = OPEN, poulate with 0 to feed DET_OUT_TP R33 = OPEN Sets the corner frequency of output offset control loop high pass filter.
R33 C23
C23 = 10 nF
C1, R30 C1 = R30 =
C20
Decoupling Pin
C20 = 1 nF
JP4
Jumper for AGC mode of operation. Provides feedback from the detector output to the gain pin.
SW1
Mode SW1. LO mode puts part in negative slope mode. HI puts part in positive slope mode. AGC operation requires negative slope mode. Power down. The part is disabled when the enable pin is tied to ground.
SW2
Rev. PrB | Page 12 of 13
Preliminary Technical Data OUTLINE DIMENSIONS
AD8368
Figure 8. 8-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm x 2 mm Body (CP-8-3) Dimensions in millimeters
ORDERING GUIDE
Model AD8368ACPZ-REEL71 AD8368ACPZ-WP1,2 AD8368-EVAL Temperature Package -40C to +85C -40C to +85C Package Description 24-Lead Lead Frame Chip Scale Package 24-Lead Lead Frame Chip Scale Package Evaluation Board Package Outline CP-24-4 CP-24-4 Branding TBD TBD
1 2
Z = Pb-free part. WP = Waffle pack.
(c) 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR05907-0-1/06(PrB)
Rev. PrB | Page 13 of 13

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